1. Field of the Invention
The present invention relates to the field of processors and, more particularly, to a technique for utilizing cache memory.
2. Background of the Related Art
The use of a cache memory with a processor is well known in the computer art. A primary purpose of utilizing cache memory is to bring the data closer to the processor in order for the processor to operate on the data more efficiently. It is generally understood that memory devices closer to the processor operate faster than memory devices farther away on the data path from the processor. However, there is a cost trade-off in utilizing faster memory devices. The faster the data access, the higher the cost to store a bit of data. Accordingly, a cache memory tends to be much smaller in storage capacity than main memory, but is faster in accessing the data.
A computer system may utilize one or more levels of cache memory and allocation and de-allocation schemes implemented for the cache for various known computer systems are generally similar in practice. That is, data that is required by the processor is cached in the cache memory (or memories). If a miss occurs, then an allocation is made at the entry indexed by the access. The access can be for loading data to the processor (also known as a read operation) or storing data from the processor to memory (also known as a write operation). When the miss occurs at a given cache level, a lower level cache memory (typically the next lower level) or main memory is accessed to retrieve the required data. The cached information is retained by the cache memory until it is no longer needed, made invalid or replaced by other data, in which instances the cache entry is de-allocated.
One notable aspect of cache memory management pertains to the efficient utilization of the cache to obtain a high ratio of "hits" to "misses" (thereby minimizing the number of misses). Since a cache miss results in additional time to retrieve the data into the cache, processing cycle time can be lost waiting for this data to arrive. As processor speeds increase, the memory system, which includes the cache memory hierarchy, will also need to improve its performance so as not to impede processor performance.
One practice for improving cache memory performance has been the use of a separate miss cache to supplement the main cache memory. For example, a level one (L1) cache may employ a direct-mapping technique to provide the fastest accessing speed. However, direct-mapping can result in a high number of cache misses. Accordingly, a supplemental fully-associative cache is utilized along with the L1 cache to improve the cache performance.
For example, U.S. Pat. No. 5,261,066 (Jouppi et al.) describes the use of a small fully-associative "victim cache" which is loaded with the victim line from the direct-mapped L1 cache. As the cache lines are replaced in the L1 cache, the evicted lines are then stored in the victim cache. According to Jouppi et al., victim caching is an improvement over miss caching.
The present invention also provides for improving the cache performance at a cache level, which improves the overall system performance for caching information in a computer system.